How to transmit data bytes from an I2C master device using DMA mode to an I2C slave device using DMA mode. The peripheral is initialized with LL unitary service functions to optimize for performance and size.
This example guides you through the different configuration steps by mean of LL API to configure GPIO, DMA and I2C peripherals using two NUCLEO-C071RB.
Boards: NUCLEO-C071RB (embeds a STM32C071RB device)
- SCL Pin: PB.8 (CN5, pin 10(D15))
- SDA Pin: PB.9 (CN5, pin 9(D14))
The project is split in two parts the Master Board and the Slave Board.
Master Board : I2C1 Peripheral is configured in Master mode with DMA (Clock 400Khz). And GPIO associated to User push-button is linked with EXTI.
Slave Board : I2C1 Peripheral is configured in Slave mode with DMA (Clock 400Khz, Own address 7-bit enabled).
The user can choose between Master and Slave through “#define SLAVE_BOARD” in the “main.h” file:
The user can disable internal pull-up by opening ioc file.
For that, user can follow the procedure :
The example is updated with no pull on each pin used for I2C communication
A first program launch, BOARD SLAVE waiting Address Match code through Handle_I2C_Slave() routine. LED1 blinks quickly on BOARD MASTER to wait for user-button press.
Example execution:
Press the User push-button on BOARD MASTER to initiate a write request by Master through Handle_I2C_Master() routine. This action will generate an I2C start condition with the Slave address and a write bit condition. When address Slave match code is received on I2C1 of BOARD SLAVE, an ADDR event occurs. Handle_I2C_Slave() routine is then checking Address Match Code and direction Write. This will allow Slave to enter in receiver mode and then acknowledge Master to send the bytes through DMA. When acknowledge is received on I2C1 (Master), DMA transfer the data from flash memory buffer to I2C1 TXDR register (Master). This will allow Master to transmit a byte to the Slave. Each time a byte is received on I2C1 (Slave), DMA transfer the data from I2C1 RXDR register to RAM memory buffer (Slave). And so each time the Slave acknowledge the byte received, DMA transfer the next data from flash memory buffer to I2C1 TXDR register (Master) until Transfer completed. Master auto-generate a Stop condition when DMA transfer is achieved.
The STOP condition generate a STOP event and initiate the end of reception on Slave side. Handle_I2C_Slave() and Handle_I2C_Master() routine are then clearing the STOP flag in both side.
LED1 is On :
In case of errors, LED1 is blinking slowly (1s).
Connectivity, Communication, I2C, DMA, Master Rx, Slave Tx, Transmission, Reception, Fast mode, SDA, SCL
This example runs on STM32C071RBTx devices.
This example has been tested with NUCLEO-C071RB board and can be easily tailored to any other supported device and development board.
NUCLEO-C071RB Set-up
Launch the program. Press User push-button to initiate a write request by Master then Slave receive bytes.
In order to make the program work, you must do the following :