Use of the DMA with a timer update request to transfer data from memory to Timer Capture Compare Register 3 (TIMx_CCR3). This example is based on the STM32C0xx TIM LL API. The peripheral initialization uses LL unitary service functions for optimization purposes (performance and size).
The following configuration values are used in this example:
The objective is to configure TIM1 channel 3 to generate PWM edge aligned signal with a frequency equal to 17.57 KHz, and a variable duty cycle that is changed by the DMA after a specific number of Update DMA request.
The number of this repetitive requests is defined by the TIM1 Repetition counter, each 4 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new value defined by the aCCValue buffer.
The PWM waveform can be displayed using an oscilloscope.
Whenever a DMA transfer fails LED1 flashes with a frequency of 1 Hz.
Timers, DMA, PWM, Frequency, Duty Cycle, Waveform, Oscilloscope, Output, Signal
This example runs on STM32C071RBTx devices.
This example has been tested with NUCLEO-C071RB board and can be easily tailored to any other supported device and development board.
NUCLEO-C071RB Set-up
In order to make the program work, you must do the following :